`timescale 1ns / 1ps
// n4fpga.v - Top level module for the ECE 544 Final Project
//
// Copyright Roy Kravitz, Portland State University 2013, 2014, 2015
//
// Created By:	Roy Kravitz
// Date:		31-December-2014
// Version:		1.0
// Modified By: Abhishek Malik and RaviRaj Kokil
// Date:		15-March-2014
// Description:
// ------------
// This module provides the top level for the Getting Started hardware.
// The module assume that a PmodCLP is plugged into the JXADC and JA
// expansion ports and that a PmodENC is plugged into the JB expansion 
// port (bottom row).  
//////////////////////////////////////////////////////////////////////
module n4fpga(
    input				clk,			// 100Mhz clock input
    input				btnC,			// center pushbutton
    input				btnU,			// UP (North) pusbhbutton
    input				btnL,			// LEFT (West) pushbutton
    input				btnD,			// DOWN (South) pushbutton  - used for system reset
    input				btnR,			// RIGHT (East) pushbutton
	input				btnCpuReset,	// CPU reset pushbutton
    input	[15:0]		sw,				// slide switches on Nexys 4
    

    output	[15:0] 		led,			// LEDs on Nexys 4   
    output              RGB1_Blue,      // RGB1 LED (LD16) 
    output              RGB1_Green,
    output              RGB1_Red,
    output              RGB2_Blue,      // RGB2 LED (LD17)
    output              RGB2_Green,
    output              RGB2_Red,
    output [7:0]        an,             // Seven Segment display
    output [6:0]        seg,
    output              dp,
    
    input				uart_rtl_rxd,	// USB UART Rx and Tx on Nexys 4
    output				uart_rtl_txd,	
    
    output	[7:0] 		JA,				// JA Pmod connector - PmodCLP control signals
										// both rows are used
    input	[7:0] 		JB,				// JB Pmod connector - PmodENC control signals
    
	output [7:0]		JC,				// JC is used to output the motor control signals
	output  [7:0]       JXADC,		    // The JXADC connector is used to connect the PMOD-CLP data bus
	input	[7:0]		JD				// JD used to take in the Hall Effect sensor inputs
);

// internal variables
wire				sysclk;
wire				sysreset_n, sysreset;
// for the rotary encoder (PMOD ENC)
wire				rotary_a, rotary_b, rotary_press, rotary_sw;
// for the LCD display (PMOD CLP)
wire	[7:0]		lcd_d;
wire				lcd_rs, lcd_rw, lcd_e;
wire    [15:0]      led_out;

wire	[7:0]	gpio_in;				// embsys GPIO input port
wire	[7:0]	gpio_out;				// embsys GPIO output port
wire            pwm_out;                // PWM output from the axi_timer
wire            clk2;

// LCD signal from the embedded system
wire    [10:0]  lcd_out;
// variables for the hall effect signals
wire            mot_hall_a;
wire            mot_hall_b;
wire            mot_hall_c;
// variables  for the motor control signals
wire    [5:0]   mot_ctl_sig;

// signal assignments as required for LCD
assign  lcd_d       = lcd_out[7:0];
assign  lcd_rs      = lcd_out[10];
assign  lcd_rw      = lcd_out[9];
assign  lcd_e       = lcd_out[8];

assign  led[15]     = led_out[15];

// reading in hall effect sensor values from JD
assign  mot_hall_a =JD[0];
assign  mot_hall_b =JD[1];
assign  mot_hall_c =JD[2];


// at JC we have the motor control signal coupled with the pwm signal
assign  JC[0]   = mot_ctl_sig[0]&pwm_out;
assign  JC[1]   = mot_ctl_sig[1];
assign  JC[4]   = mot_ctl_sig[2]&pwm_out;
assign  JC[5]   = mot_ctl_sig[3];
assign  JC[6]   = mot_ctl_sig[4]&pwm_out;
assign  JC[7]   = mot_ctl_sig[5];
//assign  JC[6]   = pwm_out;

// used for debug
assign led[5:0] = mot_ctl_sig[5:0];
assign led[14]  = pwm_out;

////////////////////////////////////////////////////////////////////////////////

//wrap the pwm_out from the timer back to the application program for software pulse-width detect
assign gpio_in = {7	'b0000000, pwm_out};

//assigning the least significant bit of the gpio_out signal to the enable signal
//this would require some significant changes in the software
//assign enable_signal = gpio_channel_1_out[0];

wire            clk_20khz;
assign clk_20khz = gpio_out[0];

// make the connections

// system-wide signals
assign sysclk = clk;
assign sysreset_n = btnCpuReset;		// The CPU reset pushbutton is asserted low.  The other pushbuttons are asserted high
										// but the microblaze for Nexys 4 expects reset to be asserted low
assign sysreset = ~sysreset_n;			// Generate a reset signal that is asserted high for any logic blocks expecting it.

// PmodCLP signals
assign JXADC = lcd_d[7:0];
assign JA[4] = lcd_rs;
assign JA[5] = lcd_rw;
assign JA[6] = lcd_e;

// PmodENC signals
assign rotary_a = JB[5];
assign rotary_b = JB[4];
assign rotary_press = JB[6];
assign rotary_sw = JB[7];

// Debug signals are on both rows of JC
wire    freq_out;
			
// instantiate the embedded system
design_final_xil EMBSYS
       (.PmodENC_A(rotary_a),
        .PmodENC_B(rotary_b),
        .PmodENC_BTN(rotary_press),
        .PmodENC_SWT(rotary_sw),
        .led_tri_o(led_out),
        .sw(sw),
        .btnCpuReset(btnCpuReset),
        .sysclk(sysclk),
        .uart_rtl_rxd(uart_rtl_rxd),
        .uart_rtl_txd(uart_rtl_txd),
        .lcd_tri_o(lcd_out),
        .Mot_Hall_A(mot_hall_a),
        .Mot_Hall_B(mot_hall_b),
        .Mot_Hall_C(mot_hall_c),
        .Mot_Ctl_Sig_tri_o(mot_ctl_sig),
        .pwm0(pwm_out),
        .clk_out2(clk2)
        );
        
endmodule

